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author | Aki <please@ignore.pl> | 2021-07-07 21:19:10 +0200 |
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committer | Aki <please@ignore.pl> | 2021-07-07 21:19:10 +0200 |
commit | ddeaee1222fc4673a40764b5db3ff6a8523fe095 (patch) | |
tree | 06d0ed9e7a434467e08eedc2b09eb872ba553185 | |
parent | 957c5d4ccf21813002f2cf37f3a9f22b5608b37b (diff) | |
download | lc3-ddeaee1222fc4673a40764b5db3ff6a8523fe095.zip lc3-ddeaee1222fc4673a40764b5db3ff6a8523fe095.tar.gz lc3-ddeaee1222fc4673a40764b5db3ff6a8523fe095.tar.bz2 |
Extended traps preparing for asm implementation
-rw-r--r-- | lc3.c | 27 |
1 files changed, 26 insertions, 1 deletions
@@ -61,6 +61,7 @@ enum Trap TRAP_OUT = 0x21, TRAP_PUTS = 0x22, TRAP_IN = 0x23, + TRAP_PUTSP = 0x24, TRAP_HALT = 0x25, }; @@ -212,7 +213,6 @@ void trap(const uint16_t instruction) die(r, "TRAP_PUTS write()"); ++w; } - fsync(0); break; } case TRAP_IN: @@ -226,8 +226,30 @@ void trap(const uint16_t instruction) registers[REGISTER_R0] = (uint16_t) c; break; } + case TRAP_PUTSP: + { + uint16_t * w = memory + registers[REGISTER_R0]; + uint8_t c; + while (*w) + { + c = (uint8_t) (*w & 0xff); + ssize_t r = write(1, &c, 1); + die(r, "TRAP_PUTSP write()"); + c = (uint8_t) (*w >> 8); + if (c) + { + r = write(1, &c, 1); + die(r, "TRAP_PUTSP write()"); + } + } + break; + } case TRAP_HALT: + { + ssize_t r = write(1, "Halt\n", 5); + die(r, "TRAP_HALT write()"); exit(EXIT_SUCCESS); + } default: exit(EXIT_FAILURE); } @@ -375,7 +397,10 @@ void step(const uint16_t instruction) break; } case OP_TRAP: + registers[REGISTER_R7] = registers[REGISTER_PC]; + registers[REGISTER_PC] = 0 | (instruction & 0xff); trap(instruction); + registers[REGISTER_PC] = registers[REGISTER_R7]; // TODO: Remove this once traps are implemented. break; case OP_RTI: case OP_RES: |