From ddeaee1222fc4673a40764b5db3ff6a8523fe095 Mon Sep 17 00:00:00 2001
From: Aki <please@ignore.pl>
Date: Wed, 7 Jul 2021 21:19:10 +0200
Subject: Extended traps preparing for asm implementation

---
 lc3.c | 27 ++++++++++++++++++++++++++-
 1 file changed, 26 insertions(+), 1 deletion(-)

diff --git a/lc3.c b/lc3.c
index 49cbd5d..c23dcce 100644
--- a/lc3.c
+++ b/lc3.c
@@ -61,6 +61,7 @@ enum Trap
 	TRAP_OUT = 0x21,
 	TRAP_PUTS = 0x22,
 	TRAP_IN = 0x23,
+	TRAP_PUTSP = 0x24,
 	TRAP_HALT = 0x25,
 };
 
@@ -212,7 +213,6 @@ void trap(const uint16_t instruction)
 				die(r, "TRAP_PUTS write()");
 				++w;
 			}
-			fsync(0);
 			break;
 		}
 		case TRAP_IN:
@@ -226,8 +226,30 @@ void trap(const uint16_t instruction)
 			registers[REGISTER_R0] = (uint16_t) c;
 			break;
 		}
+		case TRAP_PUTSP:
+		{
+			uint16_t * w = memory + registers[REGISTER_R0];
+			uint8_t c;
+			while (*w)
+			{
+				c = (uint8_t) (*w & 0xff);
+				ssize_t r = write(1, &c, 1);
+				die(r, "TRAP_PUTSP write()");
+				c = (uint8_t) (*w >> 8);
+				if (c)
+				{
+					r = write(1, &c, 1);
+					die(r, "TRAP_PUTSP write()");
+				}
+			}
+			break;
+		}
 		case TRAP_HALT:
+		{
+			ssize_t r = write(1, "Halt\n", 5);
+			die(r, "TRAP_HALT write()");
 			exit(EXIT_SUCCESS);
+		}
 		default:
 			exit(EXIT_FAILURE);
 	}
@@ -375,7 +397,10 @@ void step(const uint16_t instruction)
 			break;
 		}
 		case OP_TRAP:
+			registers[REGISTER_R7] = registers[REGISTER_PC];
+			registers[REGISTER_PC] = 0 | (instruction & 0xff);
 			trap(instruction);
+			registers[REGISTER_PC] = registers[REGISTER_R7]; // TODO: Remove this once traps are implemented.
 			break;
 		case OP_RTI:
 		case OP_RES:
-- 
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